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| Audio ICs PLL frequency synthesizer for tuners BU2618FV The BU2618FV is a low current dissipation PLL frequency synthesizer designed for use in FM multiplex radio receiver and FM pager receiver. Featuring very small package and built-in prescaler that can operate at up to 130MHz. FApplications FM multiplex radio receivers, pagers, radios, and other signal generators FFeatures 1) Built-in high-speed prescaler can divide 130 MHzVCO. 2) Low current dissipation (during operation: 1.5mA, PLL OFF: 200A Typ.) 3) Seven standard frequencies: 25kHz, 12.5kHz, 6.25kHz, 10kHz, 9kHz, 5kHz, and 1kHz. 4) 5) 6) 7) Counter for intermediate frequency detection. Unlock detection circuit. Four output ports. Serial data input (CE, CK, DA) FAbsolute maximum ratings (Ta = 25_C) FRecommended operating conditions (Ta = 25_C) 139 Audio ICs FBlock diagram BU2618FV FPin descriptions 140 Audio ICs FElectrical characteristics (unless otherwise noted, Ta = 25_C, VDD = 3.0V) BU2618FV 141 Audio ICs FCircuit operation BU2618FV 142 Audio ICs S Explanation of the data (1) Division data: For D0 through D15 (When S = 0, use D4 through D15.) BU2618FV (2) (3) (4) CT: Frequency measurement beginning data 1: Begins measurement. 0: Resets internal counter, IFIN goes to pulldown. Output port control data: 1: Open drain output ON 2: Open drain output OFF R0, R1, R2, standard frequency data (5) (6) (7) S: switch between FMIN and AMIN 0: FMIN 1: AMIN PS: If this bit is set to ON while AMIN is selected, swallow counter division is possible. GT: Frequency measurement time and unlock detection ON / OFF (8) TS: Test data (0) is input 143 Audio ICs S Frequency counter (1) Structure BU2618FV (2) How the frequency counter operates When control data CT equals 1, the 20-bit counter and the amp go into operation. When CT equals 0, amp input goes to pulldown and the counter is reset. Measuring time (gate pulse) is selected (16ms / 32ms) on the basis of control data GT. When control data CT equals 0, the counter is reset. (3) Explanation of output data D0: LSB D19: MSB Unlock detection When control data GT equals 1, or CT equals 1, the unlock detection circuit goes into operation for 8 ms. When CT equals 1, the unlock detection circuits stops operating before the frequency counter gate pulse is emitted. When CT equals 0, or GT equals 0, the unlock detection circuit is reset. 144 Audio ICs S Frequency counter and unlock detection (1) When CT = 1: Frequency count and unlock detection are carried out. BU2618FV (2) When CT = 0 and GT = 1: Only unlock detection is carried out. S Explanation of CD When frequency measurement or unlock detection is finished, the CD terminal goes to LO to indicate that the count and unlock detection have finished. It also synchronizes with CK to output counter data. When the next data is input, it goes to HI. 145 Audio ICs FElectrical characteristics curves BU2618FV FExternal dimensions (Units: mm) 146 |
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